The present invention relates to an integrated circuit design method, a database apparatus for implementing the design method and an integrated circuit design support apparatus provided with the database apparatus.
A conventional VLSI (Very Large Scale Integration) design method will be described with reference to FIG. 12. FIG. 12 is a flowchart showing an example of the conventional VLSI design method according to a top-down approach (this example referred to as "prior art" hereinafter).
In designing a VLSI, the designer firstly analyzes given design constraints, thereafter explores the architecture candidates (implementation approach), chooses the most promising one and then describes the chosen architecture by means of a hardware description language (referred to as an "HDL" hereinafter) (this description referred to as a "behavioral description" hereinafter). The thus-obtained behavioral description is a design result at the behavior level. As shown in FIG. 12(a), by subjecting this to a behavior level simulator or a verifier, the design at the behavior level is validated.
Subsequently, the designer generates a register transfer level (referred to as an "RT level" or "RTL" hereinafter) description obtained by describing an object of design at the RT level from the behavioral description (design at the RT level). The generation of the RTL description from the behavioral description is sometimes executed automatically by a behavioral synthesis tool. The generated RTL description is also a description in HDL. As shown in FIG. 12(b), by subjecting this to an RT level simulator or the like, the design at the RT level is validated. In this stage, hypothetical wire lengths are assumed for interconnections.
After the above validation, there is generated a net list (description of a logic circuit at a gate level) describing the object of design at the gate level from the RTL description by means of a logic synthesis tool. This net list is subjected to a logic simulator or the like as shown in FIG. 12(c), by which the design at the gate level is validated and a floorplan is thereafter executed. The floorplan for the net list is to roughly place and wire blocks constituting the logic circuit at the gate level.
Next, on the basis of the result of this floorplan, the design at the gate level represented by the net list is estimated. That is, a chip area, a signal delay time, a power consumption and so forth are estimated by means of the information of the placement of blocks and the wiring between blocks constituting the logic circuit, and it is decided whether or not the design constraints are satisfied. When it is decided that the design constraints are not satisfied, the net list is corrected for the design change at the gate level so that the design constraints are satisfied, and the corrected net list is subjected to the validation, floorplan and estimation similar to the above.
Thus, the processes of description change (design change by correcting the net list).fwdarw.validation.fwdarw.floorplan.fwdarw.estimation are repeated at the gate level until the design at the gate level comes to satisfy the design constraints (see FIG. 12(c)). When it is decided that the design constraints are not satisfied through the processes, there is sometimes required a return to the higher level (RT level or behavior level) at need for a design change at the higher level. In this case, the designer firstly returns to the RT level to make a description so as to change the design for the satisfaction of the design constraints. However, upon deciding that no design change can cope with the constraints, the designer further returns to the behavior level so as to correct the description data at the behavior level for a design change.
When the design at the gate level comes to satisfy the design constraints, hypothetical placement and wiring corresponding to the net list are executed by means of a cell whose internal layout has been completed. By this operation, layout data (description at a layout level) representing a layout design is obtained, and the layout data is subjected to validation, floorplan and estimation. Through the validation at the layout level, it is checked whether or not a layout design is correctly executed by means of a circuit simulator, a DRC (Design Rule Checker) and so forth. Through the floorplan at the layout level, detailed placement and wiring are executed by the aforementioned cell. Then, on the basis of the results of the detailed placement and wiring, the chip area, delay time and power consumption are correctly estimated. After the confirmation that the design constraints are satisfied, it is decided whether or not there is anything to be improved among the design features represented by the chip area, delay time, power consumption and so forth. When there is anything to be improved or when it is discovered that the design constraints are not satisfied as a consequence of estimating the chip area, delay time, power consumption and so forth more correctly than in the case of the gate level on the basis of the layout data, the layout data is corrected in correspondence, and the corrected layout data is subjected to validation, floorplan and estimation.
As described above, the processes of description change (design change by correcting the layout data).fwdarw.validation.fwdarw.floorplan.fwdarw.estimation are repeated at the gate level until the design features represented by the chip area, delay time, power consumption and so forth become satisfied (see FIG. 12(d)). When it is decided that the design constraints are not satisfied through the processes, there is sometimes a return to the higher level (gate level, RT level or behavior level) at need for a design change at the higher level.
When the design at the layout level comes to satisfy the design constraints, a mask pattern is generated from the layout data. Then, by means of a mask produced on the basis of this mask pattern, a VLSI is manufactured.
According to the aforementioned prior art design method, the precise delay time and power consumption are estimated by means of the wiring information obtained through the layout design. However, the influence of the wiring on the delay time and the power consumption has been not so significant in the integrated circuit according to the conventional semiconductor manufacturing technique. Therefore, it has scarcely occurred to discover the fact that the design constraints are not satisfied at the layout level and the consequent return to the higher level for a design change, meaning that such a design change has not been a serious problem.
However, when designing with a design rule on the order of 0.35 .mu.m or 0.25 .mu.m, or so-called the deep submicron order in accordance with the development of the semiconductor manufacturing technique, the aforementioned prior art design method cannot cope with the development. That is, in an integrated circuit fabricated by the deep submicron technique, a wiring delay becomes more dominant than a gate switching delay, and a wiring capacitance also becomes dominant in regard to the power consumption. As a result, neither the delay time nor the power consumption can be accurately estimated in the designing at the higher level, and as is often the case, this requires a return from the layout level to the gate level or the RT level for a design change or a return from the gate level to the RT level or the behavior level for a design change, possibly resulting in an actual failure in completing the design.